
library ieee;
use ieee.std_logic_1164.all;
use work.mystd.all;
use ieee.numeric_std.all;

entity PCBlock is 
	port (
    	clk		: in std_logic;		-- signal takta
    	reset	: in std_logic;		-- RESET signal

    	PCin	: in std_logic;		-- signal kojim se azurira PC
    	PCout   : in std_logic;		-- upisuje na PCvalueALUin
    	incPC   : in std_logic;		-- signal kojim se inkrementira PC

    	M3Bus	: inout bus32		-- interna magistrala PC
	); 
     
end PCBlock;     
        

architecture PCBlock of PCBlock is
	signal PCregister : bus32;        
begin

	process
	begin
		wait until clk = '1';
		
		if(reset = '1') then
			-- reset ima najvisi prioritet
			-- PC inicijalizujemo nulama
			PCregister <= X"00_00_00_00";
		else       
			if(PCin = '1') then
				-- azuriramo vrednost PC-a vrednoscu sa M3Bus
				PCregister <= M3Bus;
			elsif(incPC = '1') then
				-- inkrementiramo vrednost PC-a
				PCregister <= bus32(unsigned(PCregister) + 1);
			end if;
		end if;
	end process;
	
	-- propustamo vrednost PC-a na internu magistralu PC
	M3Bus <= PCregister when PCout = '1'
			else (others => 'Z');
			             
end PCBlock;








